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SM8213AM nippon precision circuits? nippon precision circuits inc. pocsag decoder for multiframe pagers overview the SM8213AM is a pocsag-standard (post of?e code standardization advisory group) signal processor lsi, which conforms to ccir recommen- dation 584 concerning standard international wire- less calling codes. the SM8213AM supports call messages in either tone, numerical or character outputs at signal speeds of 512, 1200 or 2400 bps. the signal input stage fea- tures a built-in ?ter. each of the addresses (max. 7 + 1 dummy = 8) can be assigned to any frame, which also makes the device con?urable for many additional services. each address can be independently set to on/off. furthermore, built-in buffer memory means decoded information can be fetched in sync with the micro- controller clock, thereby reducing the microcontrol- ler cpu time required. intermittent-duty method (battery saving (bs) method) control signals, com- patible with pll operation, and molybdenum-gate cmos structure makes possible the construction of low-voltage operation, low power dissipation sys- tems. the SM8213AM is available in 16-pin ssops. features n conforms to pocsag standard for pagers n 512, 1200 or 2400 bps signal speed n multiframe compatible (each address individually controllable) n 8 addresses 4 sub-addresses (total of 32 addresses) control (8 addresses comprise 7 actual addresses + 1 dummy address) n built-in buffer memory (1 code word) n supports tone, numeric or character call messages n built-in input signal ?ter, with ?ter on/off and 4 selectable ?ter characteristics n pll-compatible battery saving method (bs1, bs2, bs3 outputs) n bs1 (rf control main output signal) 61-step setup time setting n bs3 (pll setup signal) 61-step setup time setting n bs2 (rf dc-level adjustment signal) before/dur- ing reception selectable adjustment timing n 1-bit and 2-bit burst error auto-correction function n 25 to 75% duty factor signal coverage n 8 rate error detection condition settings n 76.8 khz system clock (crystal oscillator) n 76.8 or 38.4 khz clock output pin n built-in oscillator capacitor and feedback resistor n 2.0 to 3.5 v operating supply voltage n molybdenum-gate cmos process realizes low power dissipation n 16-pin ssop pinout top view package dimensions unit: mm attn bs1 bs2 bs3 vdd sdi sdo sck xvss xt xtn area clko vss signal rstn 8213am 1 8 9 16 0.6typ 6.8 0.3 0.8 0.36 0.1 0.4 0.2 010 0.15 + 0.10 - 0.05 0.05 0.05 1.5 0.1 4.4 0.2 6.2 0.3
SM8213AM nippon precision circuits? block diagram timing control flag register address register data comparator receive data register preamble pattern sync code idle code error correction digital pll buffer register signal area vdd vss xvss sdi sdo sck clko bs1 bs2 bs3 attn rstn xt xtn buffer register timer clock control main control circuit each working block each switch and register (ring)
SM8213AM nippon precision circuits? pin description SM8213AM paging receiver block diagram number name i/o 1 description 1 bs1 o rf control main output signal 2 bs2 o rf dc-level adjustment signal 3 bs3 o pll setup signal 4 signal i nrz signal input pin 5 xvss crystal oscillator ground. capacitor connected between xvss and vdd 6 xt i oscillator input pin 7 xtn o oscillator output pin 8 vss ground 9 clko o 76.8 or 38.4 khz clock output 10 rstn i hardware clear (reset) 11 area o sync code detection output (high for minimum 1 sec. on detection) 12 sck i cpu-to-decoder data transfer sync clock 13 sdo o status and received data output to cpu 14 sdi i data input from cpu (including id data) 15 attn o interrupt detect signal output pin (ready for data transmission when low) 16 vdd supply voltage 1. i = input, o = output rf waveform recovery pocsag decoder sp melody ic pll circuit cpu unit id rom d/d converter lcd driver lcd supply unit sm8213 alert
SM8213AM nippon precision circuits? specifications absolute maximum ratings v ss = 0 v recommended operating conditions v ss = 0 v dc characteristics recommended operating conditions unless otherwise noted parameter symbol condition rating unit supply voltage range v dd - 0.3 to 7.0 v input voltage range v in v ss - 0.3 to v dd + 0.3 v power dissipation p d 250 mw storage temperature range t stg - 40 to 125 c soldering temperature t sld 255 c soldering time t sld 10 s parameter symbol condition rating unit supply voltage range v dd 2.0 to 3.5 v operating temperature range t opr - 20 to 70 c parameter symbol condition rating unit min typ max operating current consumption (idle mode) 1 1. clko output is inactive. the consumption current is slightly higher when rstn is going low. i dd1 v dd = 3.0 v 3.0 6.0 ? v dd = 2.0 v 2.0 4.0 standby supply current 2 2. oscillator circuit is working. i dd2 v dd = 3.0 v 3.0 6.0 ? v dd = 2.0 v 2.0 4.0 high-level input voltage (all inputs) v ih 0.8v dd v low-level input voltage (all inputs) v il 0.2v dd v high-level output current (all outputs except xtn) i oh v oh = 2.6 v, v dd = 3.0 v 0.6 1.4 ma low-level output current (all outputs except xtn) i ol v ol = 0.4 v, v dd = 3.0 v 1.0 2.2 ma high-level output current (all outputs except xtn) i oh v oh = 1.6 v, v dd = 2.0 v 0.3 0.7 ma low-level output current (all outputs except xtn) i ol v ol = 0.4 v, v dd = 2.0 v 0.7 1.5 ma
SM8213AM nippon precision circuits? ac characteristics recommended operating conditions unless otherwise noted parameter/address set timing auxiliary operating mode set timing parameter symbol condition rating unit min typ max xt clock frequency f cyxt - 250 ppm 76.8 +250 ppm khz xt clock duty cycle d xt 25?5% sck clock pulsewidth t pwsc 2 150 ? sck clock interval (except write mode) t cysc 512 bps 5 1900 ? 1200 bps 5 830 2400 bps 5 415 sck clock interval (write mode) t cysc 5 830 ? sdi data setup time t ssdi 1s sdi data hold time t hsdi 1s sdo data setup time t ssdo 3s sdo data hold time t hsdo 0s attn data setup time t satt 0s attn data hold time t hatt 1s clko clock rise time t rclk no load 500 ns clko clock fall time t fclk no load 500 ns clko clock delay time d clko 1s rstn pulsewidth t pwrs 1ms attn sck sdi 12332 input data 1 input data 2 input data 3 input data 32 1/ 2*vdd t pwsc t ssdi t hsdi t cysc t hatt attn sck decoder mode sdi 128 decoder setting1 decoder setting 2 decoder setting 8 1/ 2*vdd next mode current mode t cysc t hsdi t ssdi t pwsc t hatt start command : 66 bit time max others : 2 bit time max
SM8213AM nippon precision circuits? status data read timing received data transfer timing clko clock output timing attn sck sdo sdi 1289 read command 1 read command 2 read command 8 don't care 1 don't care 2 read command 9 status data 1 1/ 2*vdd 15 16 status data 7 status data 8 read command 15 read command 16 don't care 8 t ssdo t hsdo t cysc t hsdi t ssdi t pwsc attn sck sdo sdi 12332 output data 1 output data 2 output data 3 output data 32 1/ 2*vdd t cysc t pwsc t ssdo t hsdo t satt t hatt clko (38.4khz mode) clko (76.8khz mode) 0.7*vdd 0.3*vdd 1/ 2*vdd 1/ 2*vdd 0.7*vdd 0.3*vdd t rclk t fclk t rclk t fclk (xt) (76.8khz) 0.7*vdd 0.3*vdd 1/ 2*vdd d clko ab d xt = a a+b
SM8213AM nippon precision circuits? functional description unless otherwise speci?d, values in diagrams with- out parentheses are for 512 bps, in ( ) are for 1200 bps, and in [ ] are for 2400 bps. ??represents the value of pl5 (msb) to pl0 (lsb), and ??repre- sents the value of rf5 (msb) to rf0 (lsb). receive format the receive format conforms to ccir rpc no. 1 (pocsag). sync signal (sc) the sync signal is a continuous code word in the received signal, used for word synchronization. it comprises 31 bits in an m-series bit pattern plus one even-parity bit, making a 32-bit signal. the sync code word pattern is shown in table 1. figure 1. receive signal format sync code part 1 batch frame part 01 234 567 1 code word sync code part sc sc 7 0 sync code word 1 32 address bits function bits check bits message bits 12 19 20 21 22 31 32 0 1 even - parity bit even - parity bit check bits address signal message signal 1 frame(= 2 code words) preamble 1st batch 2nd batch frame no. continuous 575 - bit "1, 0" bit pattern sync code sync code table 1. sync code format bit number bit value bit number bit value bit number bit value bit number bit value 1091170251 2 1101180261 3 1110190270 4 1121201281 5 1130210291 6 1140221300 7 0151230310 8 0160241320
SM8213AM nippon precision circuits? code words (address and message signals) each code word comprises 32 bits as shown in table 2. call number to call sign conversion this conversion expands a 7-digit decimal call num- ber into a 21-bit binary call sign, as shown in ?ure 2. after expansion, the high-order 18 bits are assigned to bits 2 to 19 (address signal), and the low-order 3 bits are the user-de?ed frame identi?ation pattern, which is stored in id-rom. the two function bits de?e which of four call functions is active. table 2. code word format code word bit number 1 (msb) 1 1. the msb is the address/message code word control bit. it is 0 for an address signal, and 1 for a message signal. 2 to 19 2 2. bits 2 to 21 contain the address or message information. 20, 21 2 22 to 31 3 3. bits 22 to 31 are bch(31,21) format generated check bits, where bch(n,k) = bch(word length, number of information bits). 32 (lsb) 4 4. the lsb is an even-parity bit for bits 1 to 31. address signal 0 address bits function bits check bits even-parity bit message signal 1 message bits check bits even-parity bit 20 21 function 0 0 a call 0 1 b call 1 0 c call 1 1 d call figure 2. call number to call sign conversion 1234567 123456789101112131415161718192021 msb lsb 7 - digit decimal call signal (gap code) (8 to 2000000) 21 - bit binary conversion call sign 0 1 2 19 20 21 32 31 22 frame identification pattern even - parity bit (for bits 1 to 31) bch(31, 21) generated check bits flag : "0" = adderss signal function bits bits 2 to 19 (18 bits) bits 22 to 31 (10 bits) p
SM8213AM nippon precision circuits? idle signal in the pocsag format, for pager systems that send numeric data, the message information content var- ies and as a result an idle signal or another address signal is inserted after the message to indicate the end of the message. that is, if no address word or message word exists for a frame within a batch or for a code word within a frame, the idle pattern, shown in table 3, is trans- mitted in its place. then during message signal reception, the message ends when the idle signal is detected. the SM8213AM supports 2 methods of determining the end of message. namely, a message ends when either an idle signal or another address is received (pocsag format), or when an interrupt signal from the cpu is received. receive signal duty factor during preamble detection, the preamble pattern (1,0) is recognized at duty factors from 25% (min) to 75% (max) of the (1,0) preamble cycle. error correction and detection the SM8213AM performs error correction (or detection) on each code word as described in table 4. note that there are 8 selectable error correction con- ditions for the preamble pattern. an error is deemed to have occurred when 2 or more signal edges occur within 1-bit unit time, and a rate error is deemed to have occurred when the number of errors exceeds the counter value. refer to the ?re- amble mode?section for a discussion of the error counter. table 3. idle code format bit number bit value bit number bit value bit number bit value bit number bit value 1091171251 2 1100181260 3 1110190270 4 1120200281 5 1131210290 6 0140220301 7 1150230311 8 0161241321 table 4. error correction item description preamble pattern detection selectable 1 to 8 rate errors in 6 to 544 bits synchronization code word detection 2 random errors in 32 bits self address code word detection 2 random errors in 32 bits message code word 1-bit and 2-bit burst errors in 31 bits
SM8213AM nippon precision circuits?0 battery saving (bs1, bs2, bs3) the SM8213AM controls the intermittent-duty oper- ation of the rf stage, which reduces battery con- sumption, and three output control signals (bs1, bs2, bs3). the function each signal controls in each mode is described below. n bs1 (rf-control main output signal)?he rf stage is active when bs1 is high. the rising- edge setup time for receive timing is set by ?gs rf0 to rf5 (61 steps). the maximum setup time is 25.417 ms at 2400 bps, 50.833 ms at 1200 bps, and 119.141 ms at 512 bps. note that 3e h and 3f h are invalid settings for bs1. n bs2 (rf dc-level adjustment signal)?s2 is used to control the discharge of the receive signal dc-cut capacitor. the function of bs2 is deter- mined by ?g bs2, as described below. when ?g bs2 is 0, pin bs2 goes high together with bs1 and then goes low again after the bs1 setup time (idle mode). in pream- ble and lock mode (during address/message reception), it stays low. when ?g bs2 is 1, pin bs2 goes high during lock mode sync code receive timing and idle mode signal receive timing. in preamble mode, it stays low. n bs3 (pll setup signal)?s3 is used to control pll operation when the pll is used. the rising- edge setup time for receive timing is set by ?gs pl0 to pl5 (61 steps). the maximum setup time is 25.833 ms at 2400 bps, 51.667 ms at 1200 bps, and 121.094 ms at 512 bps. note that 3f h is an invalid setting for bs3. note that the setup times should be set up such that (bs3 rising-edge setup time) > (bs1 rising-edge setup time). figure 3. bs1, bs2 and bs3 timing (lock mode, frame 3) syn icw mes add icw mes icw add mes mes mes mes icw icw icw add mes syn mes mes mes mes icw icw add mes mes mes mes icw add mes syn add mes 01234567 01 34567 2 01234567 01 34567 2 syn mes add syn mes mes icw icw icw icw mes mes mes mes mes mes mes mes syn mes mes mes icw add mes mes mes icw add mes icw icw icw mes mes self address 1.953*nms (0.833*nms) [0.417*nms] 1.953*mms (0.833*mms) [0.417*mms] 1.953*nms (0.833*nms) [0.417*nms] 1.953*mms (0.833*mms) [0.417*mms] break detection to reception stop (32 bit max.) receive code bs1 break command bs2 (flag bs2 option = 0) bs2 (flag bs2 option = 1) bs3 receive code bs1 bs2 (flag bs2 option = 0) bs2 (flag bs2 option = 1) bs3 address does not match self address
SM8213AM nippon precision circuits?1 operating modes the SM8213AM has four operating modes?ower- on (write), preamble, idle and lock modes. power-on mode after power is applied, the internal registers should be reset using rstn. when attn goes high, the decoder sends a write request for a decoder set read command and then waits for the microcontroller (decoder set write com- mand timing starts approximately 50 ms after reset, but you should allow at least 900 ms for the oscilla- tor internal to start and stabilize). the internal opera- tion in write mode takes place at the same timing as for 1200 bps speed mode. write data is prepared in 32-bit batches of 1 parame- ter batch and 8 address data batches for a total of 9 batches. ensure that there are not multiple writes requests to turn on the same address. also, allow a minimum of 1.67 ms after transferring each command or data before issuing the next processing command. the parameter and address set commands are pro- cessed in sync with the decoder internal clock (1200 hz). as a consequence, a gap of 28.4 ms minimum should be left between batches to provide time for processing. alternatively, data can be written by ?st using the decoder set read command to con?m whether or not processing is still in progress (busy) before writing each batch. if the time gap is 28.4 ms or greater, con?mation (ready) is not required. after parameters and all addresses have been written and after decoder processing, the decoder set start command transfers operation from write mode and starts preamble mode operation. when setting parameters and addresses in write mode, the sck clock frequency should not be less than 1200 hz. if this occurs, the sck counter is rein- itialized. this function, however, does make restor- ing operation easy even if this or another clock is accidentally input. in write mode, after power is applied and after reset initialization, all 9 batches (1 parameter and 8 address batches) should be set. if not all batches are set, subsequent operation may become unstable. figure 4. power-on mode timing busy rstn sck sdi sdo busy write mode preamble mode : 8-bit unit time data : 8-bit unit time clock : 8-bit unit time indeterminate data dat a dat a read ready start read dat a : 32-bit unit time parameter/address data ready read refer to the ac characteristics section for detailed timing specifications. max. 28.4ms 1 ms min max 900ms 129ms max 129ms max max. 1.67ms
SM8213AM nippon precision circuits?2 preamble mode preamble mode is a continuous 544-bit long period. if neither a preamble pattern, rate error nor sync code is detected during this period, operation transfers to idle mode. if a preamble pattern is detected, the preamble mode 544-bit long period is recommenced. if the sync code is detected, area goes high and operation transfers to lock mode. if an error of 2 bits or less occurs, the detected word is recognized as the sync code. during the preamble mode interval, bs1 and bs3 are held high. bs2 stays low. note that a single error occurs when two active edges occur in the received signal on signal within 1-bit unit time. a rate error occurs when the number of errors in the error counter equals the error threshold set by ?gs er0 to er2. the error counter is reset when a preamble pattern is detected. idle mode in idle mode, a check is made for the presence of a preamble signal when the rf intermittent-duty con- trol signals (bs1, bs2, bs3) for battery saving are active. if a preamble pattern is detected, operation immediately transfers to preamble mode. if a pream- ble pattern is not detected, intermittent-duty opera- tion continues. a preamble pattern is detected when either a 101010 or 010101 6-bit pattern is detected. since there is a reasonable probability that this simple pattern can occur during a valid communicated signal (data, not preamble), this 6-bit pattern makes returning to pre- amble mode easier. this is useful for cases where weak electric ?lds, noise or other temporary inter- ference cause device operation to transfer to idle mode. furthermore, the idle mode receive timing immedi- ately after transfer from lock mode is the same as the original sync code receive timing. as a result, if a sync code is detected, operation returns to lock mode. figure 5. preamble mode internal operation ..1010111010101010.. preamble signal preamble count starts counting count reset to 0 preamble detected preamble count restarts error bit t t : 1-bit time tttttt error counter (e. g. set value 3 3) preamble and error count starts preamble detected and count reset 1 010101 0 111220 figure 6. idle mode timing bs2 (flag bs2 option = 0) bs1 62.5ms (26.7ms) [13.4ms] 1062.5ms (453.3ms) [226.7ms] receive timing 1.953*nms (0.833*nms) [0.417*nms] 1.953*mms (0.833*mms) [0.417*mms] bs2 (flag bs2 option = 1) bs3
SM8213AM nippon precision circuits?3 lock mode (dummy address setting is disabled) if the sync code is detected during the preamble period, device operation transfers to lock mode and bs1 goes low. bs1 then goes high again under frame timing, where the frame number is set by ?gs ff0 to ff2, and the 28 addresses are compared with id-rom (if the frame number is 0, bs1 stays high). if errors of 2 bits or less occur, the address is still recognized. since there are two code words per frame, this check is done twice. when one of the 28 addresses does not match, bs1 goes low and the device waits for the next frame or sync code receive timing. if the sync code is still not detected after two consecutive attempts, device oper- ation transfers to idle mode, except during message reception where operation stays in lock mode. if the sync code is not detected on the second attempt, but instead a pattern forming a preamble is detected, device operation transfers to preamble mode and not idle mode (preamble mode is more advantageous for sync code detection). when one of the 28 addresses does match, attn goes low and the 32-address information (see ?ata/flags?section) is transmitted to the cpu on sdo in sync with the sck clock. when the address information is con?med to be a message, bs1 is held high and the message is received. the received message is stored in a buffer as 32-bit error-corrected information (see ?ata/flags?section), then attn goes low and the data is transmitted to the cpu on sdo in sync with the sck clock. when the address and message is received, attn should be held low while the data is output on sdo. when an incoming message spans two or more batches, additional sync code detection occurs dur- ing sync code receive timing. message reception can be selected to end when either an address code or idle code is detected, or when interrupted using the decoder set command break input. this selection is made when setting parameters that will not cause the message to termi- nate. if the break mode is selected, even if an address other than the self address (msb = 0) is received during message reception, reception contin- ues without interruption and address data is sent to the microcontroller using the same data handling as for a message. in this case, reception can only be interrupted by a break input signal from the microcontroller. in either of the above cases, message reception ends if an end-of-message signal is sent. note that if the device address is received, the end-of-message data is not transmitted. when message reception ends, bs1 goes low and the device waits for either the address detect timing of the next frame or the sync code receive timing. when sending data from the decoder to the micro- controller, the sck clock frequency should not be less than 512, (1200), [2400] hz. if this occurs, the sck counter is reinitialized. this function, however, does make restoring operation easy even if this or another clock is accidentally input. figure 7. operating mode transition diagram preamble mode lock mode idle mode b c d e a power-on mode g f h a: after reset, parameters/addresses are set and start command is issued. b: rate error or, within a fixed period, preamble pattern/sync code not detected. c: preamble pattern detected. d: sync code detected 1 cycle immediately after transfer from lock mode. e: sync code not detected on 2 consecutive attempts f: same as e, but preamble detected on the second attempt. g: sync code detected. h: parameters/addresses are set and start command is issued from preamble/idle/lock mode.
SM8213AM nippon precision circuits?4 lock mode (dummy address setting is enabled) if the sync code is detected during the preamble period, device operation transfers to lock mode and bs1 goes low. bs1 then goes high again under frame timing, where the frame number is set by ?gs ff0 to ff2, and the 28 addresses and dummy address are compared with id-rom (if the frame number is 0, bs1 stays high). if errors of 2 bits or less occur in the 28 addresses, the address is still rec- ognized. since there are two code words per frame, this check is done twice. when all of the 28 addresses do not match, bs1 goes low and the device waits for the next frame or sync code receive timing. if the sync code is still not detected after two consecutive attempts, device oper- ation transfers to idle mode, except during message reception where operation stays in lock mode. if the sync code is not detected on the second attempt, but instead a pattern forming a preamble is detected, device operation transfers to preamble mode and not idle mode (preamble mode is more advantageous for sync code detection). when one of the 28 addresses does match, attn goes low and the 32-address information (see ?ata/flags?section) is transmitted to the cpu on sdo in sync with the sck clock. the dummy address is compared in the same way as normal addresses, but regardless of the comparison result after being compared in the assigned frame, the dummy address is recognized as the device address (even if it occurs within a message). it is always recognized as the device address when it appears in either the ?st or second code word of the assigned frame. however, if addresses a to g are used at the same time dummy addressing is enabled, frames with dummy addresses should not be speci- ?d. if frames with a dummy address are speci?d, the same frame will receive two addresses, and the data transferred to the microcontroller will always be the data corresponding to the dummy address, even if one of the addresses is not a dummy address. when the normal address and dummy address infor- mation is con?med to be a message, bs1 is held high and the message is received. the received message is stored in a buffer as 32-bit error-corrected information (see ?ata/flags?section), then attn goes low and the data is transmitted to the cpu on sdo in sync with the sck clock. when the address and message is received, attn should be held low while the data is output on sdo. when an incoming message spans two or more batches, additional sync code detection occurs dur- ing sync code receive timing. message reception can be selected to end when either an address code or idle code is detected, or when interrupted using the decoder set command break input. this selection is made when setting parameters that will not cause the message to termi- nate. if the break mode is selected, even if an address other than the self address (msb = 0) is received during message reception, reception contin- ues without interruption and address data is sent to the microcontroller using the same data handling as for a message. in this case, reception can only be interrupted by a break input signal from the microcontroller. therefore, when dummy address (in combination with normal addresses) handling is enabled and parameters that will not cause the message to termi- nate are selected, this means that the device can be used in various radio and test equipment for business applications. in either of the above cases, message reception ends if an end-of-message signal is sent. note that if the device address is received, the end-of-message data is not transmitted. when message reception ends, bs1 goes low and the device waits for either the address detect timing of the next frame or the sync code receive timing. when sending data from the decoder to the micro- controller, the sck clock frequency should not be less than 512, (1200), [2400] hz. if this occurs, the sck counter is reinitialized. this function, however, does make restoring operation easy even if this or another clock is accidentally input. refer to ?ure 7 in the ?ock mode (dummy address setting is disabled)?section.
SM8213AM nippon precision circuits?5 address/parameter data transmission (cpu to SM8213AM) after device reset initialization, the address and parameter data is transmitted from the cpu in 32-bit batches, 1 parameter batch and 8 address batches for a total of 9 batches (288 bits), on sdi in sync with the falling edge of the sck clock (see ?ower-on mode?section). the SM8213AM supports 8 independent addresses (7 normal addresses: a, b, c, d, e, f, g and h + 1 dummy address: h). also, each address can be assigned a frame number to cover all kinds of group calls or subsidiary services. any of the 8 addresses can be individually disabled using the address enable??g when setting the addresses. conversely, is less than 7 addresses are used, then the use of address h is restricted and as a result the device can be used as a normal decoder. the address data for each of the 8 addresses com- prises an 18-bit address plus two function bits used to select one of four sub-addresses. then, one msb bit (0 for address signals), ten bch(31,21) format generated check bits and an even-parity bit are added to form 32-bit code word representing the address information which is then stored in ram. this address information is then compared with the received data to determine correct addressing. ensure that there are not multiple writes requests to turn on the same address. even if the number of addresses used is less than 8, all addresses should be set immediately after power is applied and immediately after reset. if not all addresses are set, subsequent operation may become unstable. each address is 18 bits long and should be input msb ?st. refer to the ac characteristics?section for sck and data speci?ations, and the ?ata/flags?section for data and ?g functions. when setting parameters and addresses in write mode, the sck clock frequency should not be less than 1200 hz. if this occurs, the sck counter is rein- itialized. this function, however, does make restor- ing operation easy even if this or another clock is accidentally input. figure 8. address/parameter transmit timing busy attn sck sdi sdo busy write mode preamble mode : 8-bit unit time data : 8-bit unit time clock : 8-bit unit time indeterminate data dat a dat a read ready start write read dat a : 32-bit unit time parameter/address data max 28.4ms refer to the ac characteristics section for detailed timing specifications. 2bit time max 1.67ms max 129ms max 129ms max
SM8213AM nippon precision circuits?6 received data transmission (SM8213AM to cpu) in lock mode, if the receive data for the frame is rec- ognized as one of the 28 normal addresses or a dummy address with 2 bit errors or less, then the data is temporarily stored in the transmit buffer and then error correction and other processing takes place. after processing, attn goes low to inform the cpu that transmit ready data is available. the SM8213AM switches the data internally and then outputs 32-bit data, shown in table 7, on sdo in sync with the falling edge of the sck clock. the cpu can then read the data on either the sck rising edge or the falling edge. the message bits (1 to 20), which are the 13th to 32nd bits of the detected address data, comprises 18 address information bits and 2 function bits. when the 32-bit transmission ends, attn goes high to indicate that all necessary information has been transmitted. when an address is detected, the next 32-bit data code word is received. the bch(31,21) format error check bits are checked and if a 1-bit or two consecu- tive bit errors occur, they are corrected. two random bit errors, or three or more bit errors are not cor- rected. if the corrected data msb is 1, the data is recognized as a message, data reception continues and the cor- rected message data and error check ?gs are sent to the cpu as 32-bit data, shown in table 7, with the same data handling as an address. in this case also, attn goes low after processing to inform the cpu that transmit ready data is available. the time from when attn goes low until the cpu sends the sck should be the same as shown in ?ure 9. also, when the message continues, the normal sck clock speed becomes faster than the receive signal bit rate and as a result there is a limit to the transmitted information capacity. as attn is used as the trans- mit ready data available signal output, it can be used as the cpu interrupt signal to receive data with the timing shown in ?ure 9. conversely, when the decoder takes attn low to indicate transmit ready data is available, the micro- controller operates under normal starting conditions (high-speed clock operation), and 32-bit clock is input on sck. after data is read in and until attn goes low for the next transmit ready data signal, the series processing should be such that it takes less than {32 (bit rate)} time. if it takes longer than this amount of time, the succeeding data may not be out- put correctly. when the msb is 0 and data is recognized as an idle signal or idle code, data reception and data transfer to the cpu stops after the end-of-message is output for addresses not matching the self address. however, when cpu break input interrupt end-of- message method is selected (see ?lag setting?sec- tion), data is treated as a message and reception con- tinues even if the msb is 0. when sending data from the decoder to the micro- controller, the sck clock frequency should not be less than 512, (1200), [2400] hz. if this occurs, the sck counter is reinitialized. this function, however, does make restoring operation easy even if this or another clock is accidentally input. figure 9. received data transmit timing attn sck sdo data data data : 8-bit 4-byte = 32-bit unit time clock : 8-bit 4-byte = 32-bit unit time data refer to the ac characteristics section for detailed timing specifications. 0ms min 32 bit time 0ms min
SM8213AM nippon precision circuits?7 decoder set command transfer (cpu to SM8213AM) in the SM8213AM, the break, back-up, write, bs- test, start and end auxiliary modes are control sig- nals from the cpu. these modes are set by data writ- ten on sdi in sync with the sck clock (see ?ata/flags?section). allow a minimum of 1.67 ms after transferring each command or data before issuing the next processing command in write mode. in other modes, allow a minimum of 4.0 (1.67) [0.9] ms. when sending data from the decoder to the micro- controller, the sck clock frequency should not be less than 1200 hz when in write mode. in other modes, the frequency should not be less than 512 (1200) [2400] hz. if this occurs, the sck counter is reinitialized. this function, however, does make restoring operation easy even if this or another clock is accidentally input. note that read mode function is described in the ?ecoder internal status transfer section. break this is the interrupt command to stop reception and data transfer. when the break command is detected, the received code word ends and reception stops, then the device waits for self frame address detection or sync code detection timing. reception may con- tinue for up to 32-bit units of time after the break command is received (or 34-bit time after the break command is sent). even though message reception may continue for a short time when the break command is sent, sync code detection does not take place and accordingly the received data may be deemed to have many errors. also, when cpu break input interrupt end-of- message method only is selected, message reception continues even if an address code or an idle code is present, as long as the break command is not issued. the time required from when the break command is issued until received data is output can be approxi- mately 2 to 3 code words at internal sync speed. dur- ing this interval, 32 clock cycles are sent to the decoder while attn is low, and processing should be performed just as for normal operation. if no pro- cessing is performed, subsequent operation may become unstable. back-up (power save control) this is the decoder off mode command. this com- mand stops all internal operation except the oscilla- tor, and thus is used to control current consumption. (the decoder internal status is write mode). note that in back-up mode, the input/output pins do not become high impedance. back-up mode is released and operation restarts when the decoder set start command is issued. all parameter and address information is retained during back-up, so operation starts directly from preamble mode. write this is the parameter and address write command. this operation mode can also be used to modify parameters and addresses. write mode can be acti- vated from bs-test mode, and also approximately 50 ms after reset, but you should allow at least 900 ms for the oscillator internal to start and stabilize. parameters and addresses can be changed by ?st issuing a decoder set command to enter write mode and then writing new parameters and addresses. note that in write mode, all internal operation takes place with the same timing as for 1200 bps speed mode. bs1, bs2 and bs3 are held low. each of the addresses can be turned on/off, according to ?g settings in the data written. using this feature for a speci? address in a pager allows the service provider, by prior agreement, to prohibit improper use of the pager delivery service (exclud- ing delivery testing, stopping subsidiary services and similar functions). in the SM8213AM, data writes from the microcon- troller have priority, even if a received information transmit ready signal (attn = low) is present (forced write). when reception from the decoder rf stage has prior- ity, operation switches to write mode after the end- of-message is con?med by monitoring the internal operation using the read command. then the param- eter set commands and address set commands are written. after writing, write mode is released using the decoder set start command, and operation starts from preamble mode.
SM8213AM nippon precision circuits?8 bs-test this mode is used to test the rf stage operation, and is only available from write mode. bs1 and bs3 are held high for rf stage testing. after testing, bs-test mode is released using the decoder set start command, and operation starts from preamble mode. note that issuing the back-up command is prohib- ited in bs-test mode. start this command is used to return to normal operation from back-up, write and bs-test modes. operation always restarts from preamble mode. note the following points when setting commands: n immediately after attn goes low commands send 8 sck clock cycles to the decoder and the received data is sent using 32 clock cycles immediately after attn goes low. however, apart from the 8 clock cycles needed for the command, 32 clock cycles are needed to release attn. note that during this time, there is no guarantee of data. n when attn is high after command is transferred and until attn goes low for the next transmit ready data signal, the series processing should be such that it takes less than {32 (bit rate)} time. if it takes longer than this amount of time, the command setting may be delayed (relative to normal operation) when attn goes low. note that during this time, there is no guarantee of data. when attn goes high (excluding write mode), sck is examined to determine if the signal is a break, back-up, write or read command. during mes- sage reception, attn is temporarily held high if a command is issued to set attn low. this delay ensures that the data from the decoder is not misin- terpreted. and in this case, even if attn keeps low, transmitted receiving data is unstable. figure 10. auxiliary operating mode timing sck sdi : 8-bit 1-byte = 8-bit unit time clock : 8-bit 1-byte = 8-bit unit time data decoder setting data current mode next mode decoder mode refer to the ac characteristics section for detailed timing specifications. start command : 66 bit time max others : 2 bit time max
SM8213AM nippon precision circuits?9 decoder internal status transfer (SM8213AM to cpu) in the SM8213AM, the internal decoder status and parameter/address end-of-processing con?mation, is transmitted to the cpu. the microcontroller uses this status information only when needed. this is a 2-byte (16 bits) command where the ?st byte is a decoder set read command and the second byte is the decoder internal status that is sent to the microcontroller in sync with the sck clock. the microcontroller can use this function when not receiving data from the decoder (when attn is high only). note the following points when setting the read com- mand: n when attn is high after data is transferred and until attn goes low for the next transmit ready data signal, the series processing should be such that it takes less than {32 (bit rate)} time. if it takes longer than this amount of time, the command setting may be delayed (relative to normal operation) when attn goes low. note that during this time, there is no guarantee of data. when attn goes high (excluding write mode), sck is examined to determine if the signal is a break, back-up, write or read command. during mes- sage reception, attn is temporarily held high if a command is issued to set attn low. this delay ensures that the data from the decoder is not misin- terpreted. and in this case, even if attn keeps low, transmitted receiving data is unstable. figure 11. internal status transfer timing attn sck sdo sdi : 8-bit 2-byte = 16-bit unit time clock : 8-bit 1-byte = 8-bit unit time data : 8-bit 1-byte = 8-bit unit time indeterminate data read status data refer to the ac characteristics section for detailed timing specifications. indicates indeterminate data output. when the cpu interprets the internal status, these portions can be ignored (discarded).
SM8213AM nippon precision circuits?0 miscellaneous interface pins signal nrz-format signal input pin, with built-in noise can- celler ?ter. current pager systems operate at 3 baud rates (512, 1200 and 2400 bps). in conventional systems, the rf stage lpf time constants are changed in response to the baud rate in order to get the best possible recep- tion. however, this requires switching the external components which results in increased product oper- ating costs. the SM8213AM, however, performs digital process- ing on the input signal which allows the 3 baud rates to be covered without the need to substitute rf stage lpf components. the side effect of this digital ?ter processing is a small probability of rate errors occur- ring. digital processing can be turned on/off using ?gs. when turned on, there are 4 ?ter constant set- tings that can be selected to obtain the best possible reception conditions in a ?xible manner (see ?arameter flags?section). xt, xtn crystal oscillator element connection pins. the SM8213AM operates at 76.8 khz system clock speed, and this clock can be provided simply by con- necting a crystal element between xt and xtn. the oscillator ampli?r, feedback resistance and oscilla- tor capacitance are all built-in. in this case, xtn should not be used as a clock to drive an external device. also, a 1000 pf to 0.1 ? capacitor should be con- nected between xvss and vdd. clko clock output pin. the clock output can be used as a cpu sleep clock or melody ic (sm1124 series) clock. the output clock frequency, 76.8 or 38.4 khz, is selected using the decoder parameter set command. rstn decoder ic internal initialization reset pin. it also functions as an oscillator start-up booster (current source) immediately after power is applied to speed up oscillator stabilization. area this pin goes high for 3 1 second when a sync code is detected with 2 or less random bit errors in preamble, lock or idle mode sync code detection tim- ing. during intermittent-duty cpu operation, monitoring this pin is useful for out-of-range signal strength. however, even if a sync code is detected, this pin is not held high for 3 1 second if 2 consecutive sync codes could not be detected, or under the following situations in 1200 and 2400 bps modes. n when the second of 2 consecutive sync codes could not be detected but a 6-bit preamble is detected and preamble continues. n when operation transfers from lock mode to idle mode and then to preamble mode. note that if operation stays in idle mode after transfer from lock mode, this pin goes high for 3 1 second.
SM8213AM nippon precision circuits?1 data/flags parameter set flags bits 1 to 7 these bits form the parameter set command. bit 8 this bit selects the output format of the rf dc-level adjustment signal output on bs2. when the ?s2 option??g is 0, pre-receive adjust- ment mode is selected, and bs2 goes high for a period of 1.953n ms (0.833n ms) [0.417n ms] immediately before receive timing during intermit- tent-duty operation in idle mode. bs2 is held low in preamble and lock mode. note that values without parentheses are for 512 bps, in ( ) are for 1200 bps, and in [ ] are for 2400 bps. ??represents the value set by rf5 (msb) to rf0 (lsb). when the ?s2 option??g is 1, mid-receive adjust- ment mode is selected, with different timing depend- ing on the mode. in idle mode, bs2 is held high only during inter- mittent-duty operation receive timing which is a period of 62.5 ms (26.7 ms) [13.4 ms]. in preamble mode, bs2 is held low. in lock mode, bs2 is held high during sync code receive timing. the sync code is a pocsag-format conforming signal comprising 32 bits of 16 ??and 16 ??bits to maintain energy balance so that, even for long message reception and fast-changing recep- tion conditions, it can still be detected. bit 9 end-of-message method select ?g. when 0, end of message occurs when either an idle code word or another address is received during mes- sage reception, or when a break command is issued from the cpu. when 1, end of message occurs only when a break command is issued from the cpu. so even if another address is received, the data is sent continuously to the cpu with message data handling. therefore, the signal is considered to be valid even if the service provider sends a message and not enough informa- tion is received due to signal noise. bit 10 clko output clock frequency select ?g. when 0, 76.8 khz is selected. when 1, 38.4 khz is selected. table 5. parameter set ?gs bit parameter setting ?g 10 21 30 40 50 60 70 8 bs2 option (bs2 option) 9 end of message detection 10 select clko frequency 11 kill clko 12 bit rate set 1 (brs1) 13 bit rate set 0 (brs0) 14 signal polarity 15 pl5 16 pl4 17 pl3 18 pl2 19 pl1 20 pl0 21 rf5 22 rf4 23 rf3 24 rf2 25 rf1 26 rf0 27 filter enable/ disable 28 filter 1 29 filter 0 30 error 2 (er 2) 31 error 1 (er 1) 32 error 0 (er 0)
SM8213AM nippon precision circuits?2 bit 11 clko clock output enable ?g. when 0, output is enabled. when 1, output is disabled. if clko clock output is not used, it can be useful in preventing unwanted noise generation. bits 12 to 13 receive bit rate set ?gs. bit 14 nrz input signal polarity select ?g. when 0, normal logic is selected. when 1, inverse logic is selected. bits 15 to 20 bs3 (pll setup signal) setup time set ?gs. ??represents the value of pl5 (msb) to pl0 (lsb) and is used to control the receive timing setup time before bs3 rising edge. the setup time is 1.953m ms (0.833m ms) [0.417m ms]. the valid values are from 2 to 62 (61 steps). note that 3f h is an invalid setting. bits 21 to 26 bs1 (rf control main output signal) setup time set ?gs. ??represents the value of rf5 (msb) to rf0 (lsb) and is used to control the receive timing setup time before bs3 rising edge. the setup time is 1.953n ms (0.833n ms) [0.417n ms]. the valid val- ues are from 2 to 62 (61 steps). note that 3e h and 3f h are invalid settings. note also that the setup times should be set such that (bs3 rising-edge setup time) > (bs1 rising-edge setup time). bit 27 nrz signal input noise canceller ?ter on/off ?g. when 0, ?ter is off. when 1, ?ter is on. bits 28 to 29 these bits set the noise canceller ?ter on-state (strength) when the ?ter is turned on using bit 27. bits 30 to 32 preamble mode rate error detection condition set ?gs. in preamble mode, under worst-case reception con- ditions, a single standard is used when distinguishing between noise and preamble to detect rate errors. these ?gs determine the rate error detection stan- dard. the error counter value (number of permissible rate errors) can be selected from the range 1 to 8. brs1 brs0 reception bit rate 0 0 512 bps 0 1 1200 bps 1 0 2400 bps 1 1 can't accept filter 1 filter 0 filter strength 1 1. filter on-state strength: 1 < 2 < 3 < 4 0 0 filter strength 1 0 1 filter strength 2 1 0 filter strength 3 1 1 filter strength 4 er 2 er 1 er 0 threshold 0 0 0 count = 1 0 0 1 count = 2 0 1 0 count = 3 0 1 1 count = 4 1 0 0 count = 5 1 0 1 count = 6 1 1 0 count = 7 1 1 1 count = 8
SM8213AM nippon precision circuits?3 address set flags in the SM8213AM, each of the 8 independent addresses can be assigned a frame. address settings are made in 8 batches in write mode immediately after power is applied and immediately after reset (9 batches total, including the parameter batch). all batches should be set. if not all batches are set, subsequent operation may become unstable. also, an address setting can be modi?d during nor- mal operation, 1 address at a time, with no adverse effects. ensure that there are not multiple writes requests to turn on the same address. bits 1 to 7 these bits form the address set command. bit 8 these bits are the address (bits 9 to 32) enable ?gs. when 1, the address set by bits 9 to 32 are valid. when 0, the address set by bits 9 to 32 are invalid. bits 9 to 11 these bits are the address (bits 15 to 32) call sign set ?gs. using 8-address control, the call signs are a, b, c, d, e, f, g and h. bits 12 to 14 these bits are the address (bits 15 to 32) frame assign ?gs. any frame can be assigned individually to any of the 8 controllable addresses. up to 8 frames can be assigned. bits 15 to 32 address bits. the 18-bit address should be written with msb ?st. table 6. address set ?gs bit address setting ?g 10 21 31 40 50 60 70 8 address enable 9 address 2 (addr 2) 10 address 1 (addr 1) 11 address 0 (addr 0) 12 frame 2 (fr 2) 13 frame 1 (fr 1) 14 frame 0 (fr 0) 15 a1 16 a2 17 a3 18 a4 19 a5 20 a6 21 a7 22 a8 23 a9 24 a9 25 a11 26 a12 27 a13 28 a14 29 a15 30 a16 31 a17 32 a18 addr 2 addr 1 addr 0 name 000a 001b 010c 011d 100e 101f 110g 111h fr 2 fr 1 fr 0 frame 0 0 0 frame 0 0 0 1 frame 1 0 1 0 frame 2 0 1 1 frame 3 1 0 0 frame 4 1 0 1 frame 5 1 1 0 frame 6 1 1 1 frame 7
SM8213AM nippon precision circuits?4 received data bit 1 the receive data leading bit is always 1. bit 2 message/address indicator ?g. when 0, the data is an address. when 1, the data is a message. bit 3 self address indicator ?g. when 1, the data is treated as a self address (device address). when 0, the data is a message. when this bit is set to 1, the self address corresponds to one of the addresses indicated by bits 4 to 6. bits 4 to 6 address call sign ?gs. when bit 3 of data is 1, indicating a self address, these bits indicate the call sign. when the data is a message, all 3 bits are set to 0. bits 7 to 8 function bit ?gs. when bit 3 of data is 1, indicating a self address, these bits set the call function for the address indi- cated by bits 4 to 6. however, when a dummy address is received (address h), bits 7 and 8 are both set to 0. when the data is a message, both bits are set to 0. table 7. receive data format bit reception data 11 2 message/ address 3 self address 4 address 2 (addr 2) 5 address 1 (addr 1) 6 address 0 (addr 0) 7 function 1 (func 1) 8 function 0 (func 0) 9 syn - val 10 error 1 (err 1) 11 error 0 (err 0) 12 parity error 13 message 1/address 1 14 message 2/address 2 15 message 3/address 3 16 message 4/address 4 17 message 5/address 5 18 message 6/address 6 19 message 7/address 7 20 message 8/address 8 21 message 9/address 9 22 message 10/address 10 23 message 11/address 11 24 message 12/address 12 25 message 13/address 13 26 message 14/address 14 27 message 15/address 15 28 message 16/address 16 29 message 17/address 17 30 message 18/address 18 31 message 19/function 1 32 message 20/function 0 addr 2 addr 1 addr 0 name 000a 001b 010c 011d 100e 101f 110g 111h func 1 func 0 function 0 0 a call 0 1 b call 1 0 c call 1 1 d call
SM8213AM nippon precision circuits?5 bit 9 sync code preceding data reception receive status ?g. when 1, indicates that there are 2 or less random bit errors. this ?g is useful in determining data reliability. bits 10 to 11 received message (or address) error correction indi- cator ?gs. note that 2-bit random errors and 3-bit (or more) errors are not corrected. when the transmitted data is an address, a 2-bit ran- dom error condition is indicated when bits 10 and 11 are both 1. bit 12 parity error indicator ?g. when 1, indicates a parity error. when 0, indicates no parity error. bits 13 to 32 message (or address) bits. these bits represent the message (or address) con- tent, output with msb ?st. end-of-message data these bits represent data at the end of a message (including when using the break command). the end-of-message data is as follows: bits 1 to 3 all 3 bits are set to 1. bits 4 to 8 all 5 bits are set to 0. bit 9 sync code preceding data reception receive status ?g. when 1, indicates that there are 2 or less random bit errors. bits 10 to 12 these bits are unknown data to be ignored. bits 13 to 32 all bits are set to 0. err 1 err 0 condition 0 0 no errors 0 1 1-bit error 1 0 2-bit continuous (burst) error 1 1 2-bit random or 3-bit (or more) error
SM8213AM nippon precision circuits?6 summary the following table show the address, message and end-of-message data formats, respectively. note that in table 7-1, bits 7 and 8 are both 0 if a dummy address (address h) is used. table 7-1. address data format bit reception data 11 20 31 4 address 2 (addr 2) 5 address 1 (addr 1) 6 address 0 (addr 0) 7 function 1 (func 1) 8 function 0 (func 0) 9 syn - val 10 error 1 (err1) 11 error 0 (err)) 12 parity error 13 address 1 14 address 2 15 address 3 16 address 4 17 address 5 18 address 6 19 address 7 20 address 8 21 address 9 22 address 10 23 address 11 24 address 12 25 address 13 26 address 14 27 address 15 28 address 16 29 address 17 30 address 18 31 function 1 32 function 0 table 7-2. message data format bit reception data 11 21 30 40 50 60 70 80 9 syn - val 10 error 1 (err 1) 11 error 0 (err 0) 12 parity error 13 message 1 14 message 2 15 message 3 16 message 4 17 message 5 18 message 6 19 message 7 20 message 8 21 message 9 22 message 10 23 message 11 24 message 12 25 message 13 26 message 14 27 message 15 28 message 16 29 message 17 30 message 18 31 message 19 32 message 20 table 7-3. end-of-message format bit reception data 11 21 31 40 50 60 70 80 9 syn - val 10 unknown 11 unknown 12 unknown 13 0 14 0 15 0 16 0 17 0 18 0 19 0 20 0 21 0 22 0 23 0 24 0 25 0 26 0 27 0 28 0 29 0 30 0 31 0 32 0
SM8213AM nippon precision circuits?7 decoder set flags these ?gs set the auxiliary operating modes. see ?ecoder set command transfer?for a description of each auxiliary operating mode. note that the start command is accepted when in back-up, write, or bs-test mode. the start command is not accepted in modes other than these three. also note that the write command is invalid in write mode. bits 1 to 2 and bit 8 these bits form the decoder set command. only one of bits 3 to 7 can be logic 1 at any given time to select the corresponding auxiliary operating mode. if more than one bit is 1 at any time, operation may become unstable. bit 3 break mode (command) ?g. when 1, break mode operation is invoked. bit 4 back-up mode (command) ?g. when 1, back-up mode operation is invoked. bit 5 write mode (command) ?g. when 1, write mode operation is invoked. bit 6 bs-test mode (command) ?g. when 1, bs-test mode operation is invoked. bit 7 start mode (command) ?g. when 1, start mode operation is invoked. table 8. decoder set ?gs bit decoder setting ?g 11 20 3 break 4 back - up 5 write 6 bs - test 7start 80
SM8213AM nippon precision circuits?8 read command set flags/data read command bits 1 to 16 these bits form the decoder read command. bits 1 to 8 form the actual command, and bits 9 to 16 are dummy data. while command bits 1 to 8 are being set, data may be output on sdo and can be treated as indeterminate data and ignored. while bits 9 to 16 are being set, however, data output on sdo is valid data. internal status bit 1 (read command bit 9) internal status output data leading bit. this bit is always 0. internal status bit 2 (read command bit 10) area pin condition ?g (when reading internal sta- tus data). when 0, area is low. when 1, area is high. internal status bit 3 (read command bit 11) decoder status ?g. when 1, decoder is operating in idle mode. internal status bit 4 (read command bit 12) decoder status ?g. when 1, decoder is operating in preamble mode. internal status bit 5 (read command bit 13) decoder status ?g. when 1, decoder is operating in lock mode. internal status bit 6 (read command bit 14) decoder status ?g. when 1, decoder is operating in write mode. internal status bit 7 (read command bit 15) decoder status ?g. when 1, decoder is receiving self address or mes- sage. internal status bit 8 (read command bit 16) decoder status ?g. when 1, indicates data write operation to the decoder internal ram (busy in write mode). do not write data when this ?g is set to 1. after each 32-bit data is written, ready con?ma- tion is not required before writing subsequent data if a space of 28.4 ms maximum is provided. table 9. read command format/internal status data bit read command bit internal status 1 11 1 0 20 2 area 30 3 idle mode 40 4 preamble mode 50 5 lock mode 60 6 write mode 70 7 adet+mdet (receiving) 81 8 busy/ ready 9090 10 0 10 area 11 0 11 idle mode 12 0 12 preamble mode 13 0 13 lock mode 14 0 14 write mode 15 0 15 adet+mdet (receiving) 16 0 16 busy/ ready 1. = indeterminate data, = determinate data
SM8213AM nippon precision circuits?9 lock mode timing examples figure 12. self frame 3 and 4 figure 13. self frame 3 and 7 (1) figure 14. self frame 3 and 7 (2) syn icw mes add icw mes icw add mes mes mes mes icw icw icw add mes syn mes mes mes mes icw add mes mes mes add mes mes mes icw syn add mes 01234567 01 34567 2 syn syn 1.953*nms (0.833*nms) [0.417*nms] 1.953*mms (0.833*mms) [0.417*mms] 1.953*nms (0.833*nms) [0.417*nms] 1.953*mms (0.833*mms) [0.417*mms] receive code bs1 bs2 (flag bs2 option = 0) bs2 (flag bs2 option = 1) bs3 address does not match self address syn - val (internal flag) : valid received sync code with 2 or less random bit errors. : invalid sync code syn icw mes add icw mes icw icw add mes mes mes icw icw icw add mes syn mes mes mes mes icw add mes add mes mes mes mes mes mes syn add mes 01234567 01 34567 2 receive code bs1 bs2 (flag bs2 option = 0) bs2 (flag bs2 option = 1) bs3 address does not match self address syn - val (internal flag) self address address does not match 01234567 01 34567 2 syn mes add syn mes mes icw icw icw icw mes mes mes mes mes mes mes mes syn mes mes mes icw add mes mes mes icw add mes icw icw icw mes mes self address break detection to reception stop (32 bit time max.) break (internal flag) receive code bs1 bs2 (flag bs2 option = 0) bs2 (flag bs2 option = 1) bs3 syn - val (internal flag)
SM8213AM nippon precision circuits?0 preamble, idle, and lock mode signal flow wrq : write mode request sync : sync code detect pre : preamble detect error : rate error detect sfr=0 : self frame number "0" syn - val : sync code detection flag preamble pl sync can not detect but detect preamble sync detect write start preamble detect write sync detect sync can not detect preamble can not detect idle id lock lk write write write idle lock preamble pl t counter reset t counter reset t counter reset t counter reset y n bs1= 1 bs3= 1 y y y y y n n n n wrq t counter increment pre error t = 543 counter reset syn - val = 1 sfr = 0 sync bs1 = 0 bs3 = 0 bs1 = 0 bs3 = 0 bs1 = 0 bs3 = 0 bs1 = 0 bs3 = 0 n
SM8213AM nippon precision circuits?1 wrq : write mode request sync : sync code detect pre : preamble detect sfr=0 : self frame number "0" syn - val : sync code detection flag t counter reset bs1 = 1 bs3 = 1 t counter reset bs1 = 0 bs3 = 0 t counter reset bs1 = 1 bs3 = 1 t counter reset bs1 = 0 bs3 = 0 reception timing preamble detection reception end pre sfr = 0 syn - val = 1 sync write idle lock preamble id t counter reset bs1 = 0 bs3 = 0 bs1 = 1 bs3 = 1 wrq t counter increment bs3 timing bs1 timing y n y n n n n y y y y n n n y y
SM8213AM nippon precision circuits?2 wrq : write mode request sync : sync code detect pre : preamble detect breaker : break command request sfr=0 : self frame number "0" syn - val : sync code detection flag adet : self address detection flag mdet : self message detection flag t counter reset t counter reset preamble idle bs1 = 0 bs3 = 0 just before self frame y n n y mdet = 1 mdet pre address add/mes bs1 0 1 message other frame code word end other frame check y n n y t = 543 sync syn - val sfr= 0 syn - val = 1 syn - val = 0 n y 1 0 mdet= 1 mdet adet= 0 not self address add/mes just before sync code just before sync code y n n 1 0 address message y address self frame code word end bs1 self frame check 1 0 t counter increment breakr mdet= 0 wrq bs3 timing bs1 timing bs1= 1 bs3= 1 write syn - val = 0 t counter reset bs1= 0 bs3= 0 mdet = 0 y n n y y n n y n n y 1 0 lock lk bs1 = 0 bs3 = 0 bs1 = 0 bs3 = 0 bs1 = 0 bs3 = 0 y just before sync code adet = 1 sync code check n y mdet= 0
SM8213AM nippon precision circuits?3 nippon precision circuits inc. reserves the right to make changes to the products contained in this data sheet in order to impr ove the design or performance and to supply the best possible products. nippon precision circuits inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no licence under any patent or other rights, and makes no claim that the circ uits are free from patent infringement. applications for any devices shown in this data sheet are for illustration only and nippon precision circuits inc. makes no claim or warranty that such applications will be suitable for the use speci?d without further testing or modi?ation. products contained in this datasheet are not intended to be the devices which may directly affect human lives due to failure or malfunct ion. customers are requested to consult with the sales department of nippon precision circuits inc. prior to considering our product s in such a special case. nippon precision circuits inc. 4-3, fukuzumi 2-chome koto-ku, tokyo 135-8430, japan telephone: 03-3642-6661 facsimile: 03-3642-6698 nc9724be 1999.01 nippon precision circuits inc.

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